A SystemVerilog Primer - Paperback
$134.93
Skip to product information
A SystemVerilog Primer - Paperback
$134.93
by J. Bhasker (Author)
This book is an excellent resource to get up to speed on the application of the various features of SystemVerilog per IEEE 1800-2009. The explanations of each feature is provided with examples and guidelines, where appropriate. This book is well organized and full of concrete examples that illustrates well on how to use SystemVerilog. It is a must primer for anyone who is beginning to learn SystemVerilog.
Author Biography
J. Bhasker is an Architect at eSilicon Corporation. Prior to that, he was a Distinguished Member of Technical Staff at Bell Laboratories. He has received a Meritorius Service Award from IEEE Computer Society for his technical contributions and continued leadership in the development of the EDA standards, especially the VHDL and Verilog RTL synthesis standards.
Number of Pages: 350
Dimensions: 0.73 x 9.25 x 7.52 IN
Publication Date: May 23, 2018
Details
This product is crafted with quality materials to ensure durability and performance. Designed with your convenience in mind, it seamlessly fits into your everyday life.
Shipping & Returns
We strive to process and ship all orders in a timely manner, working diligently to ensure that your items are on their way to you as soon as possible.
We are committed to ensuring a positive shopping experience for all our customers. If for any reason you wish to return an item, we invite you to reach out to our team for assistance, and we will evaluate every return request with care and consideration.
